The present invention relates to the manufacture of semiconductors and more specifically relates to the manufacture of dynamic random access memory (DRAM) arrays.
The integration of semiconductor devices for very large semiconductor integration (VLSI) requires that the devices first be fabricated so that they are electrically isolated from each other. Ultimately, these devices must be electrically interconnected to provide the desired circuit functionality. Thus, interconnection structures (e.g. wiring, word lines (WLs), bit lines (BLs), etc.) and contact structures, between the interconnection structures and the semiconductor devices, must also be formed.
Semiconductor memory chips, such as dynamic random access memory (DRAM), typically include array regions, including arrays of memory cells, as well as support regions, which include logic devices that provide support functionality. As dimensions shrink to 110 nm and below, DRAM technologies face several critical challenges. The cell design must be xe2x80x9cfriendlyxe2x80x9d for lithography and for the use of self-alignment techniques in the array. For example, misalignment of interconnection and contact structures can result in problems such as leakage or shorts, and increased resistance, affecting both functionality and performance.
Conventional methods of forming contacts and interconnection structures involve multiple processing steps, including lithographic masks for contacts and interconnection features at the minimum lithographic dimensions (i.e. minimum feature size). Processes involving masks having minimum feature sizes are relatively costly, and the difficulty of achieving overlay of such features without misalignment between different processing levels increases.
An example of a conventional wiring and contact layout in an array region is illustrated in the plan view shown in FIG. 8A, where source/drain diffusion regions (active areas AA) 110 on a substrate are oriented along lines, and word lines 130 are formed over the substrate, running horizontally across the diffusion regions 110. Wiring lines 120 (such as bit lines) might be laid out to run parallel and overlaying the diffusion regions 110. Although it is preferable for the wiring lines 120 to be aligned over the diffusion regions 110, typically there will be some misalignment, as illustrated in FIG. 8A. Note that the illustrations are not intended to be drawn to scale, and the misalignments shown are exaggerated for illustration purposes. Contact via holes 150 may be laid out to define contact structures for connecting the wiring to diffusion regions of devices (not shown) that are formed in the substrate.
Referring to the cross-section views along lines A-Axe2x80x2 in FIG. 8B and along line B-Bxe2x80x2 in FIG. 8C, the contact structures 150 and wiring structures 120 formed by conventional processes are illustrated. Typically, contact structures 150 are formed in a dielectric layer 210 formed over the devices in the substrate 10, for example, by a damascene process. Following that, wiring structures 120 may be formed within another dielectric layer 211, again using methods known in the art, such as a damascene method. However, this sequential method of first forming the contact structures and then forming the wiring structures suffers from two disadvantages. First, there may be overlay misalignments that can result in potential functional problems and require design tolerances that tend to limit the minimum size of devices and thereby limiting densities. Such design tolerances contribute to process costs. In addition, each additional step in the processing adds significant costs.
Many different layouts for array regions may be formed, depending on the device type and other factors. For example, for some layouts, line-type contact structures may be appropriate, such as illustrated in FIG. 9A, in which the wiring lines 120 and the contact regions 150 are both arranged in a linear fashion overlaying the linear diffusion region 110. Once again, misalignment may occur, as shown in FIG. 9A and the associated cross-sections along lines A-Axe2x80x2 and B-Bxe2x80x2 in FIGS. 9B and 9C, respectively.
Divakaruni et al. (U.S. Pat. No. 6,245,651) proposed a method for creating self-aligned borderless contacts in which a first dielectric layer is formed in both the array and support regions, and then an etch stop layer is formed over the support region. The array regions include gate stacks in the first dielectric layer, and diffusion regions between the gate stacks in the substrate, to which bitline contacts are to be formed. A second dielectric layer is then deposited over the array region and the support region, which includes the etch stop layer in the support region. The second dielectric layer is patterned to define the interconnect structures. Etching of the second dielectric layer is performed to form the interconnect structures in both the array and support regions. The etch stop layer in between the first and second dielectric layers stops the etching in the support region, but allows further etching in the array region to form the contacts, which are borderless to the gate stacks and provide contact to the diffusion regions. Subsequently, the contacts and interconnect structures may be filled with a conductive material, for example, using a damascene process. However, the method of Divakaruni et al. has the disadvantage that the buried etch stop layer in the support region produces topographical anomolies that makes removal of excess conductive material difficult in the planarization step of the damascene process. In addition, the use of separate dielectric and etch stop layers in the method of Divakaruni et al. adds complexity to the processing, and tends to increase costs.
In view of the foregoing discussion, there is a need for a process for fabricating contact and interconnect structures in high-density regions of a semiconductor chip (such as in a memory array) to reduce the misalignment of contacts and interconnection structures. In addition, there is a need to reduce the cost of such processes by reducing the number of steps in the process and/or reduce the complexity and cost of masks used in such processing.
The present invention addresses the above-described need by providing a method for forming high-density self-aligned contacts and interconnect structures in a semiconductor device. A dielectric layer thick enough to contain both interconnect and contact structures is formed on a substrate. A patterned hardmask is formed on the dielectric layer to define both the interconnect and contact structures. The openings for interconnect features are first formed by partially etching the dielectric layer selective to the hardmask. A second mask (e.g., a resist) is used to define the contact openings, and the dielectric layer is etched through the second mask, also selective to the hardmask, to expose the diffusion regions to be contacted. The patterned hardmask is used to help define the contact openings. Conductive material is then deposited in the openings which results in contacts and interconnects that are self-aligned. By first forming the openings for both interconnect and contacts, savings in processing steps may be obtained.
In accordance with the present invention, a method for forming a semiconductor device comprising the steps:
providing a substrate including a support region and an array region having an array device diffusion region;
depositing a dielectric layer on said substrate;
forming a patterned hardmask on said dielectric layer, said patterned hardmask having a first opening that overlays at least a portion of said array device diffusion region;
partially etching said dielectric layer selective to said hardmask through said first opening to form a first recess in said dielectric layer;
forming a second mask having a second opening at least partially overlapping a portion of said first recess; and
subsequently etching said dielectric layer selective to said hardmask through said second opening and through said portion of said first recess,
so that said portion of said first recess is extended through said dielectric layer to form a second recess so that a corresponding portion of said array device diffusion region is exposed.
In accordance with another aspect of the present invention, the interconnect structures of the support region may be formed at the same time as the interconnect structures in the array region.
In accordance with another aspect of the present invention, after formation of the interconnect structures, the support region may be protected, for example, by a block mask, during the formation of the contact features in the array region. Subsequently, the contact features in the support region may be formed separately.
In accordance with the present invention, a semiconductor device is provided having a substrate including a device diffusion region;
a dielectric layer on said substrate;
a contact structure formed in said dielectric layer;
an interconnect structure formed in said dielectric layer over said contact structure,
so that said contact structure is in contact with said device diffusion region and in contact with said interconnect structure and wherein said contact structure and said interconnect structure are aligned with each other.
In yet another aspect according to the present invention, the semiconductor device includes an array region and a source region. For example, the array region may be an array of memory cells, such as dynamic random access memory (DRAM) cells. In another aspect, the devices in the array region may be vertical devices, or may be planar devices.
In yet another aspect according to the present invention, the device diffusion region is associated and corresponds to a gate stack having an encapsulating material (e.g., a dielectric), where the device diffusion region is adjacent to the encapsulating material so that the contact structure is borderless to the encapsulating material of the gate stack.
The novel features believed to be characteristic of this invention are set forth in the appended claims. The invention itself, however, as well as other objects and advantages thereof, may be best understood by reference to the following detailed description of an illustrated preferred embodiment to be read in conjunction with the accompanying drawings.